G-Research is Europe’s leading quantitative finance research firm. We hire the brightest minds in the world to tackle some of the biggest questions in finance. We pair this expertise with machine learning, big data, and some of the most advanced technology available to predict movements in financial markets.
The Low Latency Engineering Group is responsible for a low-latency trading system that is a critical part of a global investment platform. The group includes teams responsible for market-data, order-entry and order-execution functions.
The group has many years of experience in building low-latency software and is taking its first steps in exploring how FPGAs can be applied to trading systems. We are applying modern engineering techniques (continuous delivery, fast feedback, and collaborative development practises using git) to FPGA development. We are looking for an experienced FPGA engineer, with strong hardware skills, to help us do this.
The LLE FPGA team is a small hybrid team of software and hardware engineers. The team is responsible for its own QA, tooling and continuous delivery pipelines. The team values flexibility and willingness to collaborate on the problems.
Key responsibilities of the role include:
- RTL HDL development in SystemVerilog and VHDL.
- Writing automated test benches
- Writing scripts in Python and TCL
- Some software development in C/C++
- Building Continuous Delivery pipelines for all components
There is a wide scope for learning and development in this role, with 10% of your time at work dedicated to allowing you to explore your own ideas, and opportunities to attend training and conferences.
Who are we looking for?
The successful candidate will be an enthusiastic and capable engineer who is able to solve real-world problems in HDL and software. They will be able to work flexibly and pro-actively and be able to make complex systems work and to debug them when they don’t.
The ideal candidate will have:
- Practical experience of hardware/software co-design for FPGA-based systems
- Strong HDL development skills in one of VHDL, Verilog or SystemVerilog
- Strong system analysis and debugging skills
- Experience of working in a collaborative engineering team, preferably using a git-based development workflow (e.g. GitHub)
- Some software development skills in C or C++
- Some knowledge of scripting in a language like Python or Perl
- Effective communication skills with both technical and non-technical people
- Financial experience is useful but not required
Why should you apply?
- Highly competitive compensation plus annual discretionary bonus
- Informal dress code and excellent work/life balance
- Comprehensive healthcare and life assurance
- 25 days holiday
- 9% contributory pension scheme
- Cycle-to-work scheme
- Subsidised gym membership
- Monthly company events
- Central London office close to 5 stations and 6 tube lines